Clock signals are commonly used in many electronics circuits and for various purposes. For example, dock signals are used to trigger synchronous circuits (e.g., flip-flops) in digital circuits such as processors, memory devices, and so on. Clock signals may be generated with various types of oscillators and supporting circuitry. A clock signal continually transitions between two levels (e.g., logic high and logic low levels). The clock signal has a duty cycle that is determined by the time duration at logic high and the time duration at logic low.
The duty cycle of a dock signal is generally stated as a percentage. For example, a clock signal that has a pattern of 80% high and 20% low has an 80% duty cycle. In some applications, it may desirable that the duty cycle of a dock signal be a 50% cycle, where a 50% duty cycle has a waveform with equal high and low portions. For example, circuits that rely on both clock edges may not function properly if a 50% duty cycle dock is not applied to the circuits. Unfortunately, many types of circuits create duty cycle distortion, and it can be difficult to maintain a 50% duty cycle.